por_dtm_fifo_entry1_2_u_smxp_1_1 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_dtm_fifo_entry1_2_u_smxp_1_1 (CPM4_CMN600) Register Description

Register Namepor_dtm_fifo_entry1_2_u_smxp_1_1
Relative Address0x000050A148
Absolute Address 0x00FC50A148 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionContains DTM FIFO entry 1 data.

por_dtm_fifo_entry1_2_u_smxp_1_1 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:32razRead as zero0x0reserved
fifo_cycle_count31:16roRead-only0x0Entry cycle count bit vector 15:0
fifo_data215:0roRead-only0x0Entry data bit vector 143:128