por_dtm_fifo_entry_ready_u_smxp_0_1 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_dtm_fifo_entry_ready_u_smxp_0_1 (CPM4_CMN600) Register Description

Register Namepor_dtm_fifo_entry_ready_u_smxp_0_1
Relative Address0x000010A118
Absolute Address 0x00FC10A118 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionControls status of DTM FIFO entries.

por_dtm_fifo_entry_ready_u_smxp_0_1 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:4razRead as zero0x0reserved
ready 3:0wtcReadable, write a 1 to clear0x0Indicates which DTM FIFO entries are ready; write a 1 to clear Bit [3]: Entry 3 ready when set Bit [2]: Entry 2 ready when set Bit [1]: Entry 1 ready when set Bit [0]: Entry 0 ready when set