por_dtm_pmevcnt_u_smxp_0_0 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_dtm_pmevcnt_u_smxp_0_0 (CPM4_CMN600) Register Description

Register Namepor_dtm_pmevcnt_u_smxp_0_0
Relative Address0x000000A220
Absolute Address 0x00FC00A220 (CPM4_CMN)
Width64
TyperwNormal read/write
Reset Value0x00000000
DescriptionContains all PMU event counters (0, 1, 2, 3).

por_dtm_pmevcnt_u_smxp_0_0 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
pmevcnt363:48rwNormal read/write0x0PMU event counter 3
pmevcnt247:32rwNormal read/write0x0PMU event counter 2
pmevcnt131:16rwNormal read/write0x0PMU event counter 1
pmevcnt015:0rwNormal read/write0x0PMU event counter 0