por_dtm_pmevcntsr_u_smxp_2_1 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_dtm_pmevcntsr_u_smxp_2_1 (CPM4_CMN600) Register Description

Register Namepor_dtm_pmevcntsr_u_smxp_2_1
Relative Address0x000090A240
Absolute Address 0x00FC90A240 (CPM4_CMN)
Width64
TyperwNormal read/write
Reset Value0x00000000
DescriptionFunctions as the PMU event counter shadow register for all counters (0, 1, 2, 3).

por_dtm_pmevcntsr_u_smxp_2_1 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
pmevcntsr363:48rwNormal read/write0x0PMU event counter 3 shadow register
pmevcntsr247:32rwNormal read/write0x0PMU event counter 2 shadow register
pmevcntsr131:16rwNormal read/write0x0PMU event counter 1 shadow register
pmevcntsr015:0rwNormal read/write0x0PMU event counter 0 shadow register