por_dtm_pmu_config_u_smxp_0_0 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_dtm_pmu_config_u_smxp_0_0 (CPM4_CMN600) Register Description

Register Namepor_dtm_pmu_config_u_smxp_0_0
Relative Address0x000000A210
Absolute Address 0x00FC00A210 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionConfigures the DTM PMU.

por_dtm_pmu_config_u_smxp_0_0 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:62razRead as zero0x0reserved
pmevcnt3_input_sel61:56rwNormal read/write0x0Source to be counted in PMU counter 3; see pmevcnt0_input_sel for encodings
Reserved55:54razRead as zero0x0reserved
pmevcnt2_input_sel53:48rwNormal read/write0x0Source to be counted in PMU counter 2; see pmevcnt0_input_sel for encodings
Reserved47:46razRead as zero0x0reserved
pmevcnt1_input_sel45:40rwNormal read/write0x0Source to be counted in PMU counter 1; see pmevcnt0_input_sel for encodings
Reserved39:38razRead as zero0x0reserved
pmevcnt0_input_sel37:32rwNormal read/write0x0Source to be counted in PMU counter 0 6h00: Watchpoint 0 6h01: Watchpoint 1 6h02: Watchpoint 2 6h03: Watchpoint 3 6h04: XP PMU Event 0 6h05: XP PMU Event 1 6h06: XP PMU Event 2 6h07: XP PMU Event 3 6h10: Port 0 Device 0 PMU Event 0 6h11: Port 0 Device 0 PMU Event 1 6h12: Port 0 Device 0 PMU Event 2 6h13: Port 0 Device 0 PMU Event 3 6h14: Port 0 Device 1 PMU Event 0 6h15: Port 0 Device 1 PMU Event 1 6h16: Port 0 Device 1 PMU Event 2 6h17: Port 0 Device 1 PMU Event 3 6h18: Port 0 Device 2 PMU Event 0 6h19: Port 0 Device 2 PMU Event 1 6h1A: Port 0 Device 2 PMU Event 2 6h1B: Port 0 Device 2 PMU Event 3 6h1C: Port 0 Device 3 PMU Event 0 6h1D: Port 0 Device 3 PMU Event 1 6h1E: Port 0 Device 3 PMU Event 2 6h1F: Port 0 Device 3 PMU Event 3 6h20: Port 1 Device 0 PMU Event 0 6h21: Port 1 Device 0 PMU Event 1 6h22: Port 1 Device 0 PMU Event 2 6h23: Port 1 Device 0 PMU Event 3 6h24: Port 1 Device 1 PMU Event 0 6h25: Port 1 Device 1 PMU Event 1 6h26: Port 1 Device 1 PMU Event 2 6h27: Port 1 Device 1 PMU Event 3 6h28: Port 1 Device 2 PMU Event 0 6h29: Port 1 Device 2 PMU Event 1 6h2A: Port 1 Device 2 PMU Event 2 6h2B: Port 1 Device 2 PMU Event 3 6h2C: Port 1 Device 3 PMU Event 0 6h2D: Port 1 Device 3 PMU Event 1 6h2E: Port 1 Device 3 PMU Event 2 6h2F: Port 1 Device 3 PMU Event 3
Reserved31razRead as zero0x0reserved
pmevcnt3_global_num30:28rwNormal read/write0x0Global counter to pair with PMU counter 3; see pmevcnt0_global_num for encodings
Reserved27razRead as zero0x0reserved
pmevcnt2_global_num26:24rwNormal read/write0x0Global counter to pair with PMU counter 2; see pmevcnt0_global_num for encodings
Reserved23razRead as zero0x0reserved
pmevcnt1_global_num22:20rwNormal read/write0x0Global counter to pair with PMU counter 1; see pmevcnt0_global_num for encodings
Reserved19razRead as zero0x0reserved
pmevcnt0_global_num18:16rwNormal read/write0x0Global counter to pair with PMU counter 0 3b000: Global PMU event counter A 3b001: Global PMU event counter B 3b010: Global PMU event counter C 3b011: Global PMU event counter D 3b100: Global PMU event counter E 3b101: Global PMU event counter F 3b110: Global PMU event counter G 3b111: Global PMU event counter H
Reserved15:9razRead as zero0x0reserved
cntr_rst 8rwNormal read/write0x0Enables clearing of live counters upon assertion of snapshot
pmevcnt_paired 7:4rwNormal read/write0x0PMU local counter paired with global counter
pmevcntall_combined 3rwNormal read/write0x0Enables combination of all PMU counters (0, 1, 2, 3) NOTE: When set, pmevcnt01_combined and pmevcnt23_combined have no effect.
pmevcnt23_combined 2rwNormal read/write0x0Enables combination of PMU counters 2 and 3
pmevcnt01_combined 1rwNormal read/write0x0Enables combination of PMU counters 0 and 1
pmu_en 0rwNormal read/write0x0DTM PMU enable NOTE: All other fields in this register are valid only if this bit is set.