Field Name | Bits | Type | Reset Value | Description |
Reserved | 63:62 | razRead as zero | 0x0 | reserved |
pmevcnt3_input_sel | 61:56 | rwNormal read/write | 0x0 | Source to be counted in PMU counter 3; see pmevcnt0_input_sel for encodings |
Reserved | 55:54 | razRead as zero | 0x0 | reserved |
pmevcnt2_input_sel | 53:48 | rwNormal read/write | 0x0 | Source to be counted in PMU counter 2; see pmevcnt0_input_sel for encodings |
Reserved | 47:46 | razRead as zero | 0x0 | reserved |
pmevcnt1_input_sel | 45:40 | rwNormal read/write | 0x0 | Source to be counted in PMU counter 1; see pmevcnt0_input_sel for encodings |
Reserved | 39:38 | razRead as zero | 0x0 | reserved |
pmevcnt0_input_sel | 37:32 | rwNormal read/write | 0x0 | Source to be counted in PMU counter 0 6h00: Watchpoint 0 6h01: Watchpoint 1 6h02: Watchpoint 2 6h03: Watchpoint 3 6h04: XP PMU Event 0 6h05: XP PMU Event 1 6h06: XP PMU Event 2 6h07: XP PMU Event 3 6h10: Port 0 Device 0 PMU Event 0 6h11: Port 0 Device 0 PMU Event 1 6h12: Port 0 Device 0 PMU Event 2 6h13: Port 0 Device 0 PMU Event 3 6h14: Port 0 Device 1 PMU Event 0 6h15: Port 0 Device 1 PMU Event 1 6h16: Port 0 Device 1 PMU Event 2 6h17: Port 0 Device 1 PMU Event 3 6h18: Port 0 Device 2 PMU Event 0 6h19: Port 0 Device 2 PMU Event 1 6h1A: Port 0 Device 2 PMU Event 2 6h1B: Port 0 Device 2 PMU Event 3 6h1C: Port 0 Device 3 PMU Event 0 6h1D: Port 0 Device 3 PMU Event 1 6h1E: Port 0 Device 3 PMU Event 2 6h1F: Port 0 Device 3 PMU Event 3 6h20: Port 1 Device 0 PMU Event 0 6h21: Port 1 Device 0 PMU Event 1 6h22: Port 1 Device 0 PMU Event 2 6h23: Port 1 Device 0 PMU Event 3 6h24: Port 1 Device 1 PMU Event 0 6h25: Port 1 Device 1 PMU Event 1 6h26: Port 1 Device 1 PMU Event 2 6h27: Port 1 Device 1 PMU Event 3 6h28: Port 1 Device 2 PMU Event 0 6h29: Port 1 Device 2 PMU Event 1 6h2A: Port 1 Device 2 PMU Event 2 6h2B: Port 1 Device 2 PMU Event 3 6h2C: Port 1 Device 3 PMU Event 0 6h2D: Port 1 Device 3 PMU Event 1 6h2E: Port 1 Device 3 PMU Event 2 6h2F: Port 1 Device 3 PMU Event 3 |
Reserved | 31 | razRead as zero | 0x0 | reserved |
pmevcnt3_global_num | 30:28 | rwNormal read/write | 0x0 | Global counter to pair with PMU counter 3; see pmevcnt0_global_num for encodings |
Reserved | 27 | razRead as zero | 0x0 | reserved |
pmevcnt2_global_num | 26:24 | rwNormal read/write | 0x0 | Global counter to pair with PMU counter 2; see pmevcnt0_global_num for encodings |
Reserved | 23 | razRead as zero | 0x0 | reserved |
pmevcnt1_global_num | 22:20 | rwNormal read/write | 0x0 | Global counter to pair with PMU counter 1; see pmevcnt0_global_num for encodings |
Reserved | 19 | razRead as zero | 0x0 | reserved |
pmevcnt0_global_num | 18:16 | rwNormal read/write | 0x0 | Global counter to pair with PMU counter 0 3b000: Global PMU event counter A 3b001: Global PMU event counter B 3b010: Global PMU event counter C 3b011: Global PMU event counter D 3b100: Global PMU event counter E 3b101: Global PMU event counter F 3b110: Global PMU event counter G 3b111: Global PMU event counter H |
Reserved | 15:9 | razRead as zero | 0x0 | reserved |
cntr_rst | 8 | rwNormal read/write | 0x0 | Enables clearing of live counters upon assertion of snapshot |
pmevcnt_paired | 7:4 | rwNormal read/write | 0x0 | PMU local counter paired with global counter |
pmevcntall_combined | 3 | rwNormal read/write | 0x0 | Enables combination of all PMU counters (0, 1, 2, 3) NOTE: When set, pmevcnt01_combined and pmevcnt23_combined have no effect. |
pmevcnt23_combined | 2 | rwNormal read/write | 0x0 | Enables combination of PMU counters 2 and 3 |
pmevcnt01_combined | 1 | rwNormal read/write | 0x0 | Enables combination of PMU counters 0 and 1 |
pmu_en | 0 | rwNormal read/write | 0x0 | DTM PMU enable NOTE: All other fields in this register are valid only if this bit is set. |