por_hnf_errfr_NS_u_hnf_nid36 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_hnf_errfr_NS_u_hnf_nid36 (CPM4_CMN600) Register Description

Register Namepor_hnf_errfr_NS_u_hnf_nid36
Relative Address0x0000407100
Absolute Address 0x00FC407100 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x000048A5
DescriptionFunctions as the non-secure error feature register.

por_hnf_errfr_NS_u_hnf_nid36 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:15razRead as zero0x0reserved
CEC14:12roRead-only0x4Standard corrected error count mechanism 3b000: Does not implement standardized error counter model 3b010: Implements 8-bit error counter in por_hnf_errmisc_NS[39:32] 3b100: Implements 16-bit error counter in por_hnf_errmisc_NS[47:32]
CFI11:10roRead-only0x2Corrected error interrupt
Reserved 9:8razRead as zero0x0reserved
FI 7:6roRead-only0x2Fault handling interrupt
UI 5:4roRead-only0x2Uncorrected error interrupt
DE 3:2roRead-only0x1Deferred errors for data poison
ED 1:0roRead-only0x1Error detection