por_hnf_ppu_dyn_ret_threshold_u_hnf_nid40 (CPM4_CMN600) Register Description
| Register Name | por_hnf_ppu_dyn_ret_threshold_u_hnf_nid40 |
|---|---|
| Relative Address | 0x0000501100 |
| Absolute Address | 0x00FC501100 (CPM4_CMN) |
| Width | 64 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Configures the dynamic retention threshold for SLC and SF RAM. |
por_hnf_ppu_dyn_ret_threshold_u_hnf_nid40 (CPM4_CMN600) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 63:12 | razRead as zero | 0x0 | reserved |
| dyn_ret_threshold | 11:0 | rwNormal read/write | 0x0 | HN-F RAM idle cycle count threshold |