por_hni_pmu_event_sel_u_hnd_nid8 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_hni_pmu_event_sel_u_hnd_nid8 (CPM4_CMN600) Register Description

Register Namepor_hni_pmu_event_sel_u_hnd_nid8
Relative Address0x0000152000
Absolute Address 0x00FC152000 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionSpecifies the PMU event to be counted.

por_hni_pmu_event_sel_u_hnd_nid8 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:30razRead as zero0x0reserved
pmu_event3_id29:24rwNormal read/write0x0HN-I PMU Event 3 select; see pmu_event0_id for encodings
Reserved23:22razRead as zero0x0reserved
pmu_event2_id21:16rwNormal read/write0x0HN-I PMU Event 2 select; see pmu_event0_id for encodings
Reserved15:14razRead as zero0x0reserved
pmu_event1_id13:8rwNormal read/write0x0HN-I PMU Event 1 select; see pmu_event0_id for encodings
Reserved 7:6razRead as zero0x0reserved
pmu_event0_id 5:0rwNormal read/write0x0HN-I PMU Event 0 select 6h00: No event 6h20: RRT read occupancy count overflow 6h21: RRT write occupancy count overflow 6h22: RDT read occupancy count overflow 6h23: RDT write occupancy count overflow 6h24: WDB occupancy count overflow 6h25: RRT read allocation 6h26: RRT write allocation 6h27: RDT read allocation 6h28: RDT write allocation 6h29: WDB allocation 6h2A: RETRYACK TXRSP flit sent 6h2B: ARVALID set without ARREADY event 6h2C: ARREADY set without ARVALID event 6h2D: AWVALID set without AWREADY event 6h2E: AWREADY set without AWVALID event 6h2F: WVALID set without WREADY event 6h30: TXDAT stall (TXDAT valid but no link credit available) 6h31: Non-PCIe serialization event 6h32: PCIe serialization event NOTE: All other encodings are reserved.