por_mxp_errfr_u_smxp_0_0 (CPM4_CMN600) Register Description
Register Name | por_mxp_errfr_u_smxp_0_0 |
---|---|
Relative Address | 0x000000B000 |
Absolute Address | 0x00FC00B000 (CPM4_CMN) |
Width | 64 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x000000A1 |
Description | Functions as the error feature register. |
por_mxp_errfr_u_smxp_0_0 (CPM4_CMN600) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 63:15 | razRead as zero | 0x0 | reserved |
CEC | 14:12 | roRead-only | 0x0 | Standard corrected error count mechanism 3b000: Does not implement standardized error counter model |
CFI | 11:10 | roRead-only | 0x0 | Corrected error interrupt |
Reserved | 9:8 | razRead as zero | 0x0 | reserved |
FI | 7:6 | roRead-only | 0x2 | Fault handling interrupt |
UI | 5:4 | roRead-only | 0x2 | Uncorrected error interrupt |
DE | 3:2 | roRead-only | 0x0 | Deferred errors for data poison |
ED | 1:0 | roRead-only | 0x1 | Error detection |