por_mxp_errfr_u_smxp_0_0 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_mxp_errfr_u_smxp_0_0 (CPM4_CMN600) Register Description

Register Namepor_mxp_errfr_u_smxp_0_0
Relative Address0x000000B000
Absolute Address 0x00FC00B000 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x000000A1
DescriptionFunctions as the error feature register.

por_mxp_errfr_u_smxp_0_0 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:15razRead as zero0x0reserved
CEC14:12roRead-only0x0Standard corrected error count mechanism 3b000: Does not implement standardized error counter model
CFI11:10roRead-only0x0Corrected error interrupt
Reserved 9:8razRead as zero0x0reserved
FI 7:6roRead-only0x2Fault handling interrupt
UI 5:4roRead-only0x2Uncorrected error interrupt
DE 3:2roRead-only0x0Deferred errors for data poison
ED 1:0roRead-only0x1Error detection