por_mxp_errmisc_u_smxp_0_0 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_mxp_errmisc_u_smxp_0_0 (CPM4_CMN600) Register Description

Register Namepor_mxp_errmisc_u_smxp_0_0
Relative Address0x000000B028
Absolute Address 0x00FC00B028 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionFunctions as the miscellaneous error register. Contains miscellaneous information about deferred/uncorrected errors.

por_mxp_errmisc_u_smxp_0_0 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:59razRead as zero0x0reserved
TGTID58:48rwNormal read/write0x0Error flit target ID
Reserved47:22razRead as zero0x0reserved
OPCODE21:16rwNormal read/write0x0Error flit opcode
Reserved15razRead as zero0x0reserved
SRCID14:4rwNormal read/write0x0Error flit source ID
Reserved 3razRead as zero0x0reserved
ERRSRC 2:0rwNormal read/write0x0Error source Bits [2:1]: Transaction type 2b00: REQ 2b01: RSP 2b10: SNP 2b11: DAT Bit [0]: Port 1b0:
Port 0 1b1:
Port 1