por_mxp_p0_qos_control_u_smxp_1_1 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_mxp_p0_qos_control_u_smxp_1_1 (CPM4_CMN600) Register Description

Register Namepor_mxp_p0_qos_control_u_smxp_1_1
Relative Address0x0000508A80
Absolute Address 0x00FC508A80 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionControls QoS settings for devices connected to port 0.

por_mxp_p0_qos_control_u_smxp_1_1 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:20razRead as zero0x0reserved
p0_qos_override19:16rwNormal read/write0x0QoS override value for port 0
Reserved15:7razRead as zero0x0reserved
p0_pqv_mode 6rwNormal read/write0x0Configures the QoS regulator mode during period mode 1b0: Normal mode; QoS value is stable when the master is idle 1b1: Quiesce high mode; QoS value tends to the maximum value when the master is idle
Reserved 5razRead as zero0x0reserved
p0_reg_mode 4rwNormal read/write0x0Configures the QoS regulator mode 1b0: Latency mode 1b1: Period mode; used for bandwidth regulation
Reserved 3razRead as zero0x0reserved
p0_qos_override_en 2rwNormal read/write0x0Enables port 0 QoS override; when set, allows QoS value on inbound transactions to be overridden
Reserved 1razRead as zero0x0reserved
p0_lat_en 0rwNormal read/write0x0Enables port 0 QoS regulation when set