por_mxp_p0_qos_lat_tgt_u_smxp_2_0 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_mxp_p0_qos_lat_tgt_u_smxp_2_0 (CPM4_CMN600) Register Description

Register Namepor_mxp_p0_qos_lat_tgt_u_smxp_2_0
Relative Address0x0000808A88
Absolute Address 0x00FC808A88 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionControls QoS target latency/period (in cycles) for regulation of devices connected to port 0.

por_mxp_p0_qos_lat_tgt_u_smxp_2_0 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:12razRead as zero0x0reserved
p0_lat_tgt11:0rwNormal read/write0x0Port 0 transaction target latency/period; a value of 0 corresponds to no regulation