por_mxp_pmu_event_sel_u_smxp_2_0 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_mxp_pmu_event_sel_u_smxp_2_0 (CPM4_CMN600) Register Description

Register Namepor_mxp_pmu_event_sel_u_smxp_2_0
Relative Address0x000080A000
Absolute Address 0x00FC80A000 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionSpecifies the PMU event to be counted.

por_mxp_pmu_event_sel_u_smxp_2_0 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:32razRead as zero0x0reserved
pmu_event3_id31:24rwNormal read/write0x0XP PMU Event 3 ID; see pmu_event0_id for encodings
pmu_event2_id23:16rwNormal read/write0x0XP PMU Event 2 ID; see pmu_event0_id for encodings
pmu_event1_id15:8rwNormal read/write0x0XP PMU Event 1 ID; see pmu_event0_id for encodings
pmu_event0_id 7:0rwNormal read/write0x0XP PMU Event 0 ID Bits [7:5]: PC 3b000: REQ 3b001: RSP 3b010: SNP 3b011: DAT Bits [4:2]: Interface 3b000: East 3b001: West 3b010: North 3b011: South 3b100: Device port 0 3b101: Device port 1 Bits [1:0]: Event specifier 2b00: No event 2b01: TX flit valid; signaled when a flit is successfully transmitted 2b10: TX flit stall; signaled when flit transmission is stalled and waiting on credits 2b11: Partial DAT flit; signaled when 128-bit DAT flits could not be merged into a 256-bit DAT flit; only applicable on the DAT PC on RN-F CHIA and RN-F CHIA ESAM ports