por_ppu_qactive_hyst_u_hnd_nid8 (CPM4_CMN600) Register Description
Register Name | por_ppu_qactive_hyst_u_hnd_nid8 |
---|---|
Relative Address | 0x0000101010 |
Absolute Address | 0x00FC101010 (CPM4_CMN) |
Width | 64 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000010 |
Description | Number of hysteresis clock cycles to retain QACTIVE assertion |
por_ppu_qactive_hyst_u_hnd_nid8 (CPM4_CMN600) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 63:16 | razRead as zero | 0x0 | reserved |
hnf_ppu_qact_hyst | 15:0 | rwNormal read/write | 0x10 | QACTIVE hysteresis |