por_ppu_qactive_hyst_u_hnd_nid8 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_ppu_qactive_hyst_u_hnd_nid8 (CPM4_CMN600) Register Description

Register Namepor_ppu_qactive_hyst_u_hnd_nid8
Relative Address0x0000101010
Absolute Address 0x00FC101010 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000010
DescriptionNumber of hysteresis clock cycles to retain QACTIVE assertion

por_ppu_qactive_hyst_u_hnd_nid8 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:16razRead as zero0x0reserved
hnf_ppu_qact_hyst15:0rwNormal read/write0x10QACTIVE hysteresis