por_rni_s0_qos_lat_tgt_u_rni_nid0 (CPM4_CMN600) Register Description
| Register Name | por_rni_s0_qos_lat_tgt_u_rni_nid0 |
|---|---|
| Relative Address | 0x0000010A88 |
| Absolute Address | 0x00FC010A88 (CPM4_CMN) |
| Width | 64 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Controls QoS target latency (in cycles) for regulations of port S0 read and write transactions. |
por_rni_s0_qos_lat_tgt_u_rni_nid0 (CPM4_CMN600) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 63:28 | razRead as zero | 0x0 | reserved |
| s0_ar_lat_tgt | 27:16 | rwNormal read/write | 0x0 | Port S0 AR channel target latency; a value of 0 corresponds to no regulation |
| Reserved | 15:12 | razRead as zero | 0x0 | reserved |
| s0_aw_lat_tgt | 11:0 | rwNormal read/write | 0x0 | Port S0 AW channel target latency; a value of 0 corresponds to no regulation |