por_rni_s1_qos_lat_tgt_u_rni_nid0 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_rni_s1_qos_lat_tgt_u_rni_nid0 (CPM4_CMN600) Register Description

Register Namepor_rni_s1_qos_lat_tgt_u_rni_nid0
Relative Address0x0000010AA8
Absolute Address 0x00FC010AA8 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionControls QoS target latency (in cycles) for regulation of port S1 read and write transactions.

por_rni_s1_qos_lat_tgt_u_rni_nid0 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:28razRead as zero0x0reserved
s1_ar_lat_tgt27:16rwNormal read/write0x0Port S1 AR channel target latency; a value of 0 corresponds to no regulation
Reserved15:12razRead as zero0x0reserved
s1_aw_lat_tgt11:0rwNormal read/write0x0Port S1 AW channel target latency; a value of 0 corresponds to no regulation