Device Diagrams

Versal ACAP Packaging and Pinouts Architecture Manual (AM013)

Document ID
AM013
Release Date
2020-07-16
Revision
1.0 English

The diagrams in this chapter show top-view perspective of the package pinout of each Versal™ device/package combination. The following table is a cross reference to the device/package diagrams. The device diagram shows the location of each user I/O, PMCMIO, LPDMIO, PMCDIO, and GTY transceiver and the respective bank or GTY quad, as well as the location of every power pin in the package. See Package Specifications Designations for definitions of Evaluation Only, Engineering Sample, and Production device diagrams.

Important: All packages are available with eutectic BGA balls. To order these packages, the device type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q.
Table 1. Cross-Reference to Versal Device Diagrams by Package
Package Footprint Compatible Devices
SFVB625 VM1102

Evaluation Only

 
VBVA1024 VC1352

Evaluation Only

VC1502

Evaluation Only

 
VFVB1024 VM1102

Evaluation Only

VM1302

Evaluation Only

VM1402

Evaluation Only

 
VFVF1369 VM1302

Evaluation Only

VM1402

Evaluation Only

 
VSVE1369 VC1352

Evaluation Only

VC1702

Evaluation Only

 
VSVG1369 VC1502

Evaluation Only

   
VSVA1596 VC1502

Evaluation Only

VC1702

Evaluation Only

 
VIVA1596 VC1802

Engineering Sample

VC1902

Engineering Sample

 
VFVA1760 VM1302

Evaluation Only

VM1402

Evaluation Only

VM2602

Evaluation Only

 
VFVC1760 VM1502

Evaluation Only

VM1802

Engineering Sample

VM2602

Evaluation Only

VM2902

Evaluation Only

 
VSVD1760 VM1802

Engineering Sample

VC1802

Engineering Sample

VC1902

Engineering Sample

   
VSVA2197 VM1802

Engineering Sample

VM2502

Evaluation Only

VC1502

Evaluation Only

VC1802

Engineering Sample

VC1902

Engineering Sample