Die Level Bank Numbering Overview

Versal ACAP Packaging and Pinouts Architecture Manual (AM013)

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1.0 English

Banking and Clocking Summary

For each device, not all banks are bonded out in every package.

GTY and GTM Columns

  • One GT Quad = Four transceivers = Four GTYE5_QUAD or GTME5_QUAD primitives.
  • Not all GT Quads are bonded out in every package.
  • Also shown are quads labeled with RCAL. This specifies the location of the RCAL masters for each device. With respect to the package, the RCAL masters are located on the same package pin for each package, regardless of the device.
  • The XY coordinates shown in each quad correspond to the transceiver channel number found in the pin names for that quad (as shown in the next section).
  • An alphabetic designator is shown in each quad. Each letter corresponds to the columns in the tables in the Transceiver Footprint Compatibility between Packages section.
  • The power supply group is shown in brackets [ ] for each quad.

I/O Banks

  • Each user XPIO bank has a total of 54 I/Os that can be used as differential (27 differential pairs) or single-ended I/Os. All 54 pads of a bank are not always bonded out to pins.
  • A limited number of XPIO banks have fewer than 54 SelectIO pins. These banks are labeled as partial.
  • Each user HDIO bank has a total of 22 I/Os that can be used as pseudo-differential (11 differential pairs) or single-ended I/Os.
  • Adjacent to each bank is a physical layer (PHY) containing clock buffers and clock management resources
  • XPIO banks are arranged in rows on the north and south of the device with adjacent PHY and clock management resources.
  • XPIO banks are separated into groups of 1, 2, or 3 banks that signify how to group them when used for DDR memory controller applications.
  • I/Os in some banks on the left and right edges of the XPIO rows do not have direct access to all I/O logic resources and can only be used for DDR memory controller (DDRMC) applications. These I/Os are specified in the following device diagrams, where each XPIO bank is designated by a Y (DDRMC only) or a N (access to all I/O logic resources) for each nibble (nine nibbles per bank and six I/Os per nibble). This is also specified in the DDRMC Only column of the Package Files.
  • Global clock (GC) pins in DDRMC Only nibbles include full access to clock management resources.
  • HDIO banks are arranged in columns and separated into rows that are pitch-matched with adjacent PHY, clock management resources, and GT blocks.
  • An alphabetic designator is shown in each bank. Each letter corresponds to the columns in Table 1.


  • Each XPIO bank has four pairs of global clock (GC) inputs for four differential or four single-ended clock inputs. Single-ended clock inputs should be connected to the P-side of the differential pair.
  • Each HDIO bank has two global clock (HDGC) inputs for two single-ended clock inputs, a pseudo-differential pair or a true-differential pair for a limited selection of I/O standards.
  • Clock signals are distributed through global buffers driving routing and distribution networks to reach any clock region, I/O, or GTY transceivers.
  • Global clock inputs can connect to MMCMs and PLLs within the XPIO bank or adjacent clock management resources

Processor Blocks

  • PMC MIO pins are in banks 500 and 501
  • LPD MIO pins are in bank 502
  • PMC dedicated pins are in bank 503

PCIe, CPM, Interlaken, and 100GE Integrated Blocks

Integrated block for PCIe® . The PCIe blocks with an additional (Tandem) label support tandem configuration.
CCIX and PCIe® processor sub-system module
Interlaken block
100G Ethernet block