Differences from Previous Generations

Versal ACAP Packaging and Pinouts Architecture Manual (AM013)

Document ID
AM013
Release Date
2020-07-16
Revision
1.0 English

This section lists the differences from previous generations of the packaging and pinout specifications.

  • In addition to 0.8 mm and 1.0 mm BGA ball pitch, Versal ACAP packages have 0.92 mm BGA ball pitch, signified by a package code beginning with a V.
  • Some packages include land-side capacitor (LSC) technology (decoupling capacitors on the bottom side of the package, adjacent to the BGA balls). LSC array dimensions for each package are found in Mechanical Drawings.
  • Hardware blocks bonded to package pins have been added with Versal™ ACAPs, including XPIO, PMCMIO, and LPDMIO banks.
  • I/Os in some banks on the left and right edges of the XPIO rows do not have direct access to all I/O logic resources and can only be used for DDR memory controller (DDRMC) applications.
  • VRP pins, previously found in each HPIO bank, are replaced with a single IO_VR pin for each row of XPIO banks.
  • VCCO voltage range for XPIO banks is 1.0V to 1.5V instead of the 1.0V to 1.8V range for HPIO banks in previous generations.
  • Device diagrams showing package pinout (previously separated into I/O diagrams and power/dedicated/multifunction diagrams, are combined into a single diagram for Versal ACAP packages.
  • Package marking found on previous device generations is replaced with a 2D bar code.