Lidless Flip-Chip Packages

Versal ACAP Packaging and Pinouts Architecture Manual (AM013)

Document ID
AM013
Release Date
2020-07-16
Revision
1.0 English

The Xilinx flip-chip BGA packages exhibit a low-resistance thermal path that adequately cools devices. These packages incorporate a heat spreader lid with additional thermal interface material as shown in the following figure.

Figure 1. Flip-Chip BGA Construction with Heat Spreader and Thermal Interface Material

Materials with high thermal conductivity and consistent process applications deliver low thermal resistance up to the heat spreader. A parallel effort to ensure optimized package electrical return paths produces an enhanced power and ground plane arrangement in the package. A boost in copper density on the planes improves the overall thermal conductivity through the laminate. The extra density and distribution via fields in the package also increases the vertical thermal conductivity.

The lidless packages (see the following figure) offer the same package substrate design with electrical and board thermal conductivity similar to the flip-chip BGA packages. However, removing the lid (heat spreader) and the thermal interface material allows for direct contact between the external heat sink and the die. This further reduces the thermal resistance and exhibits improved thermal behaviors. The use of custom passive or active heat-sink designs is facilitated by incorporating two-phase (heat pipe, vapor chamber, or even liquid) cooling methods directly adjacent to the source of the dissipated heat on the die, which allows for a more efficient means of removing the heat from the device. Consequently, the device can operate at higher ambient temperatures while in area-constrained surroundings resulting in operational power advantages.

Figure 2. Lidless Flip-Chip BGA Construction

A unique feature of lidless packages is the addition of a stiffener ring around the periphery of the package substrate, providing additional package rigidity and helping to improve the overall package coplanarity (flatness). It also serves as a guide for the heat sink solution applied to the device. For examples, see the VSVD1760 Package—VC1802, VC1902, and VM1802 or VSVA2197 Package—VC1802, VC1902, and VM1802. In the lidless packages, capacitors can be placed in the area surrounding the die. Contact with electrically conductive materials must be avoided because the die-side capacitors, which are only slightly shorter than the die height, could be electrically conductive. Any thermal and mechanical solution higher than the die must not interfere with the package stiffener. Therefore, the thermal solution must have an island, see System Level Heat Sink Solutions. For further guidelines on mechanical and thermal designs of lidless packages, refer to Mechanical and Thermal Design Guidelines for Lidless Flip-Chip Packages (XAPP1301).