PMCMIO, LPDMIO, PMCDIO Pin Definitions

Versal ACAP Packaging and Pinouts Architecture Manual (AM013)

Document ID
AM013
Release Date
2020-07-16
Revision
1.0 English
Table 1. PMCMIO, LPDMIO, PMCDIO Pin Definitions
Pin Name Direction Description
PMC_MIO[0 to 51] Bidirectional Platform management controller (PMC) multiplexed I/O (MIO)
LPD_MIO[0 to 25] Bidirectional Low-power domain (LPD) MIO
MODE[0 to 3] Input The MIO MODE selection pins are used to select the boot mode of the device. The value of these pins is captured on the rising edge of POR_B.
ERROR_OUT Output The ERROR_OUT pin is open drain with a weak internal pull-up. An external pull-up is recommended. ERROR_OUT is 3-stated and pulled High when an error occurs in the device.
RTC_PADO Output Real-time clock (RTC) crystal output
RTC_PADI Input RTC crystal input
PUDC_B Input The pull-up during configuration (PUDC_B) pin is used to select the behavior of the XPIO or HDIO during configuration. If the PUDC_B pin is High, then the XPIO and HDIO are put into tristate mode. If the PUDC_B is Low, then internal pull-ups at each XPIO and HDIO are enabled. The PUDC_B pin does not affect the PS or PMC I/O during boot and configuration.
DONE Bidirectional The DONE pin is open drain with a weak internal pull-up resistor. An external pull-up is recommended. DONE is tristated and pulled High when the boot sequence is complete.
REF_CLK Input/Output The reference clock is required for all boot modes. The REF_CLK is also the input clock to the PMC PLL and is required for the slave boot interface software register access.
POR_B Input Active-Low POR_B pin is the global power-on reset for the Versal device. It must remain asserted Low until power is fully applied to at least the VCC_PMC, VCCAUX_PMC, and VCCO_503. When the reset is released, the PMC begins the initialization and boot process.
TCK Input JTAG test clock
TDI Input JTAG test data input
TDO Output JTAG test data output
TMS Input JTAG test mode select