Versal ACAP AI Engine Register Reference > Module Summary > aie_memory_module Module > DMA_BD0_Control (aie_memory_module) Register
DMA_BD0_Control (aie_memory_module) Register
DMA_BD0_Control (aie_memory_module) Register Description
Register Name | DMA_BD0_Control |
---|---|
Relative Address | 0x000001D018 |
Absolute Address |
The notation for the AI Engine register addresses is aie_memory_module_column_row.
Absolute Addresses
0x2000005D018 (aie_memory_module_0_1) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | DMA BD0 Length, Next BD, BD Count |
DMA_BD0_Control (aie_memory_module) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Valid_BD | 31 | rwNormal read/write | 0x0 | BD is valid |
Enable_AB_Mode | 30 | rwNormal read/write | 0 | Enable A and B buffer handling |
Enable_FIFO_Mode | 29:28 | rwNormal read/write | 0 | FIFO mode enabled and what FIFO counter to use (0x = No FIFO, 10=FIFO Cnt0, 11=FIFO Cnt1) |
Enable_Packet | 27 | rwNormal read/write | 0 | Add packet header to data. Only relevent to MM2S DMA |
Enabled_Interleaved | 26 | rwNormal read/write | 0 | Interleaved channel mode enabled |
Interleaved_Count | 25:18 | rwNormal read/write | 0 | Count for interleaved channels. Factor of BD Length (Actual - 1) |
Use_Next_BD | 17 | rwNormal read/write | 0 | Use next BD value. If not set, disable DMA |
Next_BD | 16:13 | rwNormal read/write | 0 | Next BD to continue with |
Length | 12:0 | rwNormal read/write | 0 | Length of Buffer (32-bits words) (Actual - 1) |