Versal ACAP AI Engine Register Reference > Module Summary > aie_core_module Module > Debug_Control1 (aie_core_module) Register
Debug_Control1 (aie_core_module) Register
Debug_Control1 (aie_core_module) Register Description
Register Name | Debug_Control1 |
---|---|
Relative Address | 0x0000032014 |
Absolute Address |
The notation for the AI Engine register addresses is aie_core_module_column_row.
Absolute Addresses
0x20000072014 (aie_core_module_0_1) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Debug Halt Event Control |
Debug_Control1 (aie_core_module) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Debug_Halt_Core_Event1 | 30:24 | rwNormal read/write | 0x0 | Event No to Halt the AI Engine |
Debug_Halt_Core_Event0 | 22:16 | rwNormal read/write | 0x0 | Event No to Halt the AI Engine |
Debug_SingleStep_Core_Event | 14:8 | rwNormal read/write | 0x0 | Event No to Single-Step the AI Engine |
Debug_Resume_Core_Event | 6:0 | rwNormal read/write | 0x0 | Event No to resume AI Engine execution after debug halt |