Versal ACAP AI Engine Register Reference > Module Summary > aie_pl_module Module > Stream_Switch_Master_Config_South1 (aie_pl_module) Register
Stream_Switch_Master_Config_South1 (aie_pl_module) Register
Stream_Switch_Master_Config_South1 (aie_pl_module) Register Description
Register Name | Stream_Switch_Master_Config_South1 |
---|---|
Relative Address | 0x000003F010 |
Absolute Address |
The notation for the AI Engine register addresses is aie_pl_module_column_row.
Absolute Addresses
0x2000003F010 (aie_pl_module_0_0) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Stream Switch Master Configuration South 1 |
Stream_Switch_Master_Config_South1 (aie_pl_module) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Master_Enable | 31 | rwNormal read/write | 0x0 | 1=enable the master port |
Packet_Enable | 30 | rwNormal read/write | 0x0 | 0=circuit; 1=packet switching mode for master port |
Drop_Header | 7 | rwNormal read/write | 0x0 | 1=drop header on packet |
Configuration | 6:0 | rwNormal read/write | 0x0 | circuit: [4:0]=slave port; packet: [2:0]=arbitor, [6:3]=msel_enable |