Tile_Clock_Control (aie_pl_module) Register

Versal ACAP AI Engine Register Reference

Document ID
AM015

Versal ACAP AI Engine Register Reference > Module Summary > aie_pl_module Module > Tile_Clock_Control (aie_pl_module) Register

Tile_Clock_Control (aie_pl_module) Register

Tile_Clock_Control (aie_pl_module) Register Description

Register NameTile_Clock_Control
Relative Address0x0000036040
Absolute Address The notation for the AI Engine register addresses is aie_pl_module_column_row.
Absolute Addresses

0x20000036040 (aie_pl_module_0_0)
0x20000836040 (aie_pl_module_1_0)
0x20001036040 (aie_pl_module_2_0)
0x20001836040 (aie_pl_module_3_0)
0x20002036040 (aie_pl_module_4_0)
0x20002836040 (aie_pl_module_5_0)
0x20003036040 (aie_pl_module_6_0)
0x20003836040 (aie_pl_module_7_0)
0x20004036040 (aie_pl_module_8_0)
0x20004836040 (aie_pl_module_9_0)
0x20005036040 (aie_pl_module_10_0)
0x20005836040 (aie_pl_module_11_0)
0x20006036040 (aie_pl_module_12_0)
0x20006836040 (aie_pl_module_13_0)
0x20007036040 (aie_pl_module_14_0)
0x20007836040 (aie_pl_module_15_0)
0x20008036040 (aie_pl_module_16_0)
0x20008836040 (aie_pl_module_17_0)
0x20009036040 (aie_pl_module_18_0)
0x20009836040 (aie_pl_module_19_0)
0x2000A036040 (aie_pl_module_20_0)
0x2000A836040 (aie_pl_module_21_0)
0x2000B036040 (aie_pl_module_22_0)
0x2000B836040 (aie_pl_module_23_0)
0x2000C036040 (aie_pl_module_24_0)
0x2000C836040 (aie_pl_module_25_0)
0x2000D036040 (aie_pl_module_26_0)
0x2000D836040 (aie_pl_module_27_0)
0x2000E036040 (aie_pl_module_28_0)
0x2000E836040 (aie_pl_module_29_0)
0x2000F036040 (aie_pl_module_30_0)
0x2000F836040 (aie_pl_module_31_0)
0x20010036040 (aie_pl_module_32_0)
0x20010836040 (aie_pl_module_33_0)
0x20011036040 (aie_pl_module_34_0)
0x20011836040 (aie_pl_module_35_0)
0x20012036040 (aie_pl_module_36_0)
0x20012836040 (aie_pl_module_37_0)
0x20013036040 (aie_pl_module_38_0)
0x20013836040 (aie_pl_module_39_0)
0x20014036040 (aie_pl_module_40_0)
0x20014836040 (aie_pl_module_41_0)
0x20015036040 (aie_pl_module_42_0)
0x20015836040 (aie_pl_module_43_0)
0x20016036040 (aie_pl_module_44_0)
0x20016836040 (aie_pl_module_45_0)
0x20017036040 (aie_pl_module_46_0)
0x20017836040 (aie_pl_module_47_0)
0x20018036040 (aie_pl_module_48_0)
0x20018836040 (aie_pl_module_49_0)

Width32
TyperwNormal read/write
Reset Value0x00000003
DescriptionControl of global clock gating

Tile_Clock_Control (aie_pl_module) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Next_Tile_Clock_Enable 1rwNormal read/write0x1Control the clock of next tile only. 1=Clock enabled; 0=Clock gated
Clock_Buffer_Enable 0rwNormal read/write0x1Contro the global clock buffer, affects all tiles above the current tile.
1=Clock enabled; 0=Clock gated