Versal ACAP AI Engine Register Reference > Module Summary > aie_pl_module Module > Tile_Clock_Control (aie_pl_module) Register
Tile_Clock_Control (aie_pl_module) Register
Tile_Clock_Control (aie_pl_module) Register Description
Register Name | Tile_Clock_Control |
---|---|
Relative Address | 0x0000036040 |
Absolute Address |
The notation for the AI Engine register addresses is aie_pl_module_column_row.
Absolute Addresses
0x20000036040 (aie_pl_module_0_0) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000003 |
Description | Control of global clock gating |
Tile_Clock_Control (aie_pl_module) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Next_Tile_Clock_Enable | 1 | rwNormal read/write | 0x1 | Control the clock of next tile only. 1=Clock enabled; 0=Clock gated |
Clock_Buffer_Enable | 0 | rwNormal read/write | 0x1 | Contro the global clock buffer, affects all tiles above the current tile. 1=Clock enabled; 0=Clock gated |