Versal ACAP AI Engine Register Reference > Module Summary > aie_core_module Module > Tile_Control_Packet_Handler_Status (aie_core_module) Register
Tile_Control_Packet_Handler_Status (aie_core_module) Register
Tile_Control_Packet_Handler_Status (aie_core_module) Register Description
Register Name | Tile_Control_Packet_Handler_Status |
---|---|
Relative Address | 0x0000036034 |
Absolute Address |
The notation for the AI Engine register addresses is aie_core_module_column_row.
Absolute Addresses
0x20000076034 (aie_core_module_0_1) |
Width | 32 |
Type | wtcReadable, write a 1 to clear |
Reset Value | 0x00000000 |
Description | Status of control packet handling |
Tile_Control_Packet_Handler_Status (aie_core_module) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Tlast_Error | 3 | wtcReadable, write a 1 to clear | 0x0 | Sticky bit |
SLVERR_On_Access | 2 | wtcReadable, write a 1 to clear | 0x0 | Sticky bit |
Second_Header_Parity_Error | 1 | wtcReadable, write a 1 to clear | 0x0 | Sticky bit |
First_Header_Parity_Error | 0 | wtcReadable, write a 1 to clear | 0x0 | Sticky bit |