This chapter describes the various components in CPM for CCIX operation. The
CCB (Cache Coherency Block) specifies CPM cache and coherency architecture. CCB is the
CCIX gateway to on-chip and off-chip processing nodes and memory. The CCIX gateway
capabilities are achieved by a combination of the CHI-B and PCI Express transport
interconnect. The transport requirements for the integrated block for PCI Express
specific to CCIX have been covered in CCIX Capable PCIe Controller.
This chapter describes the other blocks in detail. The following figure shows the
architectural details of the CPM block. For information on clock speeds, refer to data
sheet.
Figure 1. CPM Block Diagram
The CCB manages coherency between local accelerators (in programmable logic) and
other CCIX devices including the host. There are two CHI-B interfaces exposed to the
programmable logic for accelerator connectivity to the CCB. The first CHI-B port
connects to the CCB via the asynchronous CPI module and L2 cache. The second CHI-B
interface connects to the CCB vis the asynchronous CPI module. There are two memory
ports (AXI4 interfaces) from the CCB that connect (via the PS) to the NoC and then to
the DDR.