CCIX PER Message

Versal ACAP CPM CCIX Architecture Manual (AM016)

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1.1 English
The CCIX Protocol Error message (PER) is supported through CCIX Transport Vendor Specific Extended Capability (DVSEC) located in Function #0. This capability is in PCI configuration space starting at byte address 0xDBC (DWORD/register address 0x36F). The Capability registers are shown in the following figure.
Note: This region is accessed by the firmware running on the VersalĀ® device to generate PER messages. This is not to be used by the host side software.
Figure 1. PER Message Capability (Non Optimized TLP Format)

Control register (byte address 0xDC8), bit 0, is PER Message Send. Writing a 1 to this register asserts cfg2tl_ccix_per_msg_send to the transaction layer, sending the PER message. Reads to this register always return 0. Status register, (byte address 0xDC4), bit 0, is PER Message Send Complete. This bit is set by the signal tl2cfg_ccix_per_msg_send_done from the transaction layer. Writing a 1 to this register clears the status. When a 1 is written to the PER Message Send register bit, the contents of the Packet Header, PER Header, and PER Payload registers are sent by the transaction layer. The non-optimized TLP format is shown in the following figure.

For optimized TLPs, the Packet Header Byte#0 to Byte#3 (byte address 0xDD8) is sent (as shown in the following figure), along with the PER Header and PER Payload. The PER Header bytes and PER Payload bytes are from section 14.6.5 PER message of the CCIX Protocol specification.

Figure 2. PER Message Capability (Optimized TLP Format)