CCIX Transport and Protocol DVSEC layout is shown in the following figure.
Figure 1. CCIX DVSEC
The CCIX Transport and Protocol DVSEC layout is implemented in the PCIe extended space area of the configuration space, as defined in the Versal ACAP CPM Mode for PCI Express Product Guide (PG346). CCIX Transport DVSEC is implemented in Physical Function #0 only, whereas CCIX Protocol DVSEC is implemented in both Physical Function #0 (PF0) and Physical Function #1 (PF1).