CMN Topology

The CMN is a scalable mesh network of interconnect to which different agents in the CHI protocol can be attached. The following figure shows the CMN topology in the CPM. The numbers adjacent to each agent in the figure indicate node id.

Figure 1. CMN Topology in the CPM

XP (crosspoint) is a switch and router logic unit and the fundamental component of the CMN interconnect. Each XP unit consists of four interconnect ports to connect to adjacent XP units and two device ports to connect to the different agents in the CHI. As shown in the figure, the CMN has six XP units configured as a 3x2 mesh network. RN-F refers to a fully coherent requesting node, HN-F refers to a fully coherent home node, and HN-D refers to the device which includes the I/O home node, DVM node, and configuration node.

Note: The CMN does not support data check (parity) on the CHI interfaces and the CXS interfaces. Because of this the CPM does not provide end-to-end parity protection for CCIX use cases.

Important: The CMN has some registers that are required to be accessed by TZ secure transactions. The Master used to access these registers should be properly configured to generate secure transactions. Refer to the CMN TRM for information on registers that need TZ access.

RN-F and CML are assigned to common a crosspoint. Sharing a crosspoint for an RN-F/CML combination allows direct connectivity (thereby avoiding mesh traversal) for the following traffic types:

Remote request traffic from accelerator kernel in the PL
Remote snoop traffic from the CCIX

This benefits both latency and bandwidth between the RN-F and CML.

HN-F provides home node functionality including snoop filters. SBSX is a CHI-to-AXI bridge that allows the CMN to connect to a memory controller. HN-F and SBSX share a crosspoint. This allows direct connectivity providing latency and bandwidth benefits to the following traffic types:

Memory traffic between HN-F and SBSX
Snoop data from HN-F

Note: Each memory port from the CCB is capable of issuing 32 cacheline size (64 byte) write transactions with unique AXI IDs per write and 64 cacheline (64 byte) read transactions with unique AXI IDs per read. Address interleaving to DDR (when CCIX is enabled) is handled by CMN-600 using address hashing. Both ports from CCB into the PS interconnect route all transactions based on address without performing interleaving.

Note: The following features are not supported:

CHI-B direct memory transfers (where the SBSX does not transfer data to the RN-F or CML, directly bypassing HN-F)
CHI-B and CXS data check
CHI-B direct cache transfer (direct transfer between the CML and RN-F when either one has a dirty copy bypassing the HN-F)
CCIX partial cache states and 128 byte cacheline support (this prevents the accelerator from using CHI-B partial opcodes)
Address-based flush by programming CMN registers directly is not supported by the curent CMN IP version. Cache- maintenance operations (CMO) should be used instead.