Clock Frequencies and Interface Widths in EDR Mode

Versal ACAP CPM CCIX Architecture Manual (AM016)
Document ID
AM016
Release Date
2020-11-24
Revision
1.1 English
Table 1. Clock Frequencies and Interface Widths
PCIe Link Speed Cap PCIe Link Width Cap AXI4 Streaming Interface Data Width (bits) user_clk2 Frequency (MHz) G1-4/E1-4/E5/E6
EDR x4 256 250/250/312.5/390.625
x8 512 500/500/625/781.25
  1. EDR mode data rates:
    1. Required Data Rates: 2.5GT/s (E1), 5.0 GT/s (E2), 8.0 GT/s (E3), 16.0 GT/s (E4), 20.0 GT/s

      (E5), and 25.0 GT/s (E6)

  2. EDR mode configurations:
    1. Initial link up in PCIe compliant mode (before transitioning to EDR mode) can be based on either x4Gen4 or x8Gen4 capabilities.
    2. Link width achieved during initial link up in PCIe compliant mode must be equal to the configured width to achieve the configured link width in EDR mode.