The CPM has an internal PLL to generate the 1.2 GHz CPM core clock. The reference clock for this PLL comes from either the PMC or the PL. It receives the other clocks from the GTx, PS, and PL. Some clocks are internally generated by dividing the CPM core clock. The clocks in the CPM are listed in the following table.
The CPM sends 2 clocks: pcie0_user_clk and pcie1_user_clk – to 2 DPLLs in the GT clocking column of the PL. Each DPLL is used to deskew the respective pcie_user_clk and the output clock from the DPLL is then used by the PL to drive/capture signals on the AXI4-ST PCIe-PL interface. The following table lists the frequencies of the clocks used in typical CCIX design. Refer to the Versal ACAP CPM Mode for PCI Express Product Guide (PG346) for details on supported frequencies in the PL for pcie0_user_clk and pcie1_user_clk. The following table emphasizes that pcie_user_clk and pl_chi_clk are asynchronous.
| Clock Name | Source |
Fmin (MHz) |
Fmax (MHz) |
Clk group | Description |
|---|---|---|---|---|---|
| pl_chi0_clk | PL | 100 | 391 | Async | Clock used by CPM-PL CHI port 0. This is generated from a PLL that resides in the PL. |
| pl_chi1_clk | PL | 100 | 391 | Async | Clock used by CPM-PL CHI port 1. This is generated from a PLL that resides in the PL. |
| pcie0_user_clk | CPM internal | 62.5 | 500 | PCIe0 | Clock for PCIe0 AXI4-stream and CFG interfaces. 500 MHz in PL is not supported |
| pcie1_user_clk | CPM internal | 62.5 | 500 | PCIe1 | Clock for PCIe1 AXI4-stream and CFG interfaces. 500 MHz in PL is not supported |