Debug Architecture

The CPM SoC Debug block interfaces with the Master SoC debug block in the PS and interacts with debug components in the CPM. The debug architecture in the CPM is based on ARM CoreSight technology. The following figure shows the various debug components in the CPM. The CPM includes an SoC Debug block that interacts with the debug components in various sub-blocks and transfers the information to the master debug block in the PS. The debug sub-system in the CPM then acts as a slave to the PS. Refer to the Versal ACAP Technical Reference Manual (AM011) for more information on SoC debug in the PS sub-system.

Figure 1. CPM Debug Architecture

CXS interfaces are observable through the extended logic analyzer (ELA). The connection details are provided in the following table.

Table 1. ELA Signal Assignment – CXS Interfaces
ELA Instance	Signal Group	Bits	CXS Signal
ELA 0	SIGNALGRP9	[0:0]	cxs_active_req_tx
ELA 0	SIGNALGRP9	[1:1]	cxs_active_ack_tx
ELA 0	SIGNALGRP9	[2:2]	cxs_deact_hint_tx
ELA 0	SIGNALGRP9	[16:3]	cxs_cntl_tx
ELA 0	SIGNALGRP9	[17:17]	cxs_valid_tx
ELA 0	SIGNALGRP9	[18:18]	cxs_crdgnt_tx
ELA 0	SIGNALGRP9	[19:19]	cxs_crdrtn_tx
ELA 0	SIGNALGRP9	[51:20]	cxs_data_chk_tx
ELA 0	SIGNALGRP9	[52:52]	cxs_cntl_chk_tx
ELA 0	SIGNALGRP9	[53:53]	cxs_valid_chk_tx
ELA 0	SIGNALGRP9	[54:54]	cxs_crdgnt_chk_tx
ELA 0	SIGNALGRP9	[55:55]	cxs_crdrtn_chk_tx
ELA 0	SIGNALGRP9	[56:56]	cxs_active_req_rx
ELA 0	SIGNALGRP9	[57:57]	cxs_active_ack_rx
ELA 0	SIGNALGRP9	[58:58]	cxs_deact_hint_rx
ELA 0	SIGNALGRP9	[72:59]	cxs_cntl_rx
ELA 0	SIGNALGRP9	[73:73]	cxs_valid_rx
ELA 0	SIGNALGRP9	[74:74]	cxs_crdgnt_rx
ELA 0	SIGNALGRP9	[75:75]	cxs_crdrtn_rx
ELA 0	SIGNALGRP9	[107:76]	cxs_data_chk_rx
ELA 0	SIGNALGRP9	[108:108]	cxs_cntl_chk_rx
ELA 0	SIGNALGRP9	[109:109]	cxs_valid_chk_rx
ELA 0	SIGNALGRP9	[110:110]	cxs_crdgnt_chk_rx
ELA 0	SIGNALGRP9	[111:111]	cxs_crdrtn_chk_rx
ELA 0	SIGNALGRP9	[159:128]	cxs_data_tx[ 31: 0]
ELA 0	SIGNALGRP9	[191:160]	cxs_data_tx[159:128]
ELA 0	SIGNALGRP9	[223:192]	cxs_data_rx[ 31: 0]
ELA 0	SIGNALGRP9	[255:224]	cxs_data_rx[159:128]
ELA 1	SIGNALGRP9	[255:0]	cxs_data_tx
ELA 2	SIGNALGRP9	[255:0]	cxs_data_rx
ELA 0	SIGNALGRP10	[0:0]	cxs_active_req_tx
ELA 0	SIGNALGRP10	[1:1]	cxs_active_ack_tx
ELA 0	SIGNALGRP10	[2:2]	cxs_deact_hint_tx
ELA 0	SIGNALGRP10	[16:3]	cxs_cntl_tx
ELA 0	SIGNALGRP10	[17:17]	cxs_valid_tx
ELA 0	SIGNALGRP10	[18:18]	cxs_crdgnt_tx
ELA 0	SIGNALGRP10	[19:19]	cxs_crdrtn_tx
ELA 0	SIGNALGRP10	[51:20]	cxs_data_chk_tx
ELA 0	SIGNALGRP10	[52:52]	cxs_cntl_chk_tx
ELA 0	SIGNALGRP10	[53:53]	cxs_valid_chk_tx
ELA 0	SIGNALGRP10	[54:54]	cxs_crdgnt_chk_tx
ELA 0	SIGNALGRP10	[55:55]	cxs_crdrtn_chk_tx
ELA 0	SIGNALGRP10	[56:56]	cxs_active_req_rx
ELA 0	SIGNALGRP10	[57:57]	cxs_active_ack_rx
ELA 0	SIGNALGRP10	[58:58]	cxs_deact_hint_rx
ELA 0	SIGNALGRP10	[72:59]	cxs_cntl_rx
ELA 0	SIGNALGRP10	[73:73]	cxs_valid_rx
ELA 0	SIGNALGRP10	[74:74]	cxs_crdgnt_rx
ELA 0	SIGNALGRP10	[75:75]	cxs_crdrtn_rx
ELA 0	SIGNALGRP10	[107:76]	cxs_data_chk_rx
ELA 0	SIGNALGRP10	[108:108]	cxs_cntl_chk_rx
ELA 0	SIGNALGRP10	[109:109]	cxs_valid_chk_rx
ELA 0	SIGNALGRP10	[110:110]	cxs_crdgnt_chk_rx
ELA 0	SIGNALGRP10	[111:111]	cxs_crdrtn_chk_rx
ELA 0	SIGNALGRP9	[159:128]	cxs_data_tx[ 31: 0]
ELA 0	SIGNALGRP9	[191:160]	cxs_data_tx[159:128]
ELA 0	SIGNALGRP9	[223:192]	cxs_data_rx[ 31: 0]
ELA 0	SIGNALGRP9	[255:224]	cxs_data_rx[159:128]
ELA 1	SIGNALGRP10	[255:0]	cxs_data_tx
ELA 2	SIGNALGRP10	[255:0]	cxs_data_rx

ELA clocks can be gated using a ela_clkgate_en bit in CPM_SLCR.DEBUG_CTRL register. By default, ELA clocks are gated. The ela_clkgate_en bit of CPM_SLCR.DEBUG_CTRL register should be programmed to a 1 prior to using ELA. The ELA 500 instance here is used to monitor and capture various flits on the CHI0 instance (between L2 and CPI) and CHI1 instance (between CMN and CPI).