CCIX architecture requires implementations to use Virtual Channel 0 (VC0) as the control channel. For more information regarding AXI4-ST data interfaces on VC0 and control and status interfaces, refer to the Versal ACAP CPM Mode for PCI Express Product Guide (PG346). All CCIX packets received via PCI Express Virtual Channel 1 (VC1) are routed internally to the CPM and to the CMN. All VC0 data and control interfaces from PCIe controllers are synchronous to the user_clk and are reset with the user_reset signal.