This architecture manual provides a detailed description of the Versal® ACAP Integrated block for PCI Express® with DMA and cache coherent interconnect (CPM) operating in CCIX mode. The integrated PCI Express controllers operate as endpoints when used in CCIX mode. This chapter introduces the CPM. For details on PCI Express functionality as root ports or with integrated DMA blocks, see the Versal ACAP CPM Mode for PCI Express Product Guide (PG346).
The CPM comprises two instances of the integrated controller for PCI Express . Both instances support CCIX capability. The CPM also contains the necessary components to allow a logic accelerator to act as a CCIX-compliant accelerator. The following figure shows the block diagram for the CPM.
The CPM connects to the transceivers, programmable logic (PL), and processing system (PS). The PS provides paths to connect to the network on chip (NoC) and to the DDR.
- Two integrated PCI Express controllers that support Gen4 with
up to x8 independent lanes. CCIX-only 20 GT/s and 25 GT/s extended data rate
(EDR) for x8 link width are also supported. Use of only one x16 Gen4 controller
is also supported.
- Virtual channel 0 (VC0) carries standard PCI Express traffic
- VC1, when enabled, carries CCIX traffic
- A cache coherence block that includes the cache coherent
interconnect and additional logic needed to connect to the CCIX port of each
integrated PCI Express controller.
- The cache coherent interconnect is realized using Coherent Mesh Network IP. For more information on the CMN-600 Coherent Mesh Network, see the Arm® CoreLink CMN-600 Coherent Mesh Network Technical Reference Manual.
- Instance of the L2 cache controller interfaces with programmable logic through the CHI-B-compliant Coherent Hub Interface.