Level 2 Cache

Versal ACAP CPM CCIX Architecture Manual (AM016)

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1.1 English

The integrated shared level-2 cache is provided to minimize the latency and bandwidth of the acceleration function in programmable logic to memory accesses. The accelerator function can implement a small level-1 cache as well.

Figure 1. CPM Shared Level 2 Cache
The L2 block with the cache controller also provides an AXI4lite interface to access the internal configuration registers. The slave port of the L2 block instance connects to the CMN on the RN-F device port. Main components of the L2 cache controller block are:
  • Physically addressable, physically tagged cache of 1 MB in size
  • Fixed cacheline size of 64 bytes
  • 48-bit physical address
  • Snoop control unit
L2 cache supports atomic transactions (on the CHI) with SnoopMe opcode enabled. Additional notes are as follows:
L2 Tag ECC double bit error interrupt
This applies to L2 cache tag and directory double-bit ECC errors. The appropriate invalidation engine is required to be triggered as part of the uncorrectable/fatal interrupt handling sequence to invalidate the contents of the tag or directory arrays.
First WriteBack request generation at L2-CMN
After the CleanInvalid request appears at the CPI-L2 interface, L2 takes about 36 clock cycles to generate the first WriteBack request at the L2-CMN interface.
Write request
L2 waits to receive the write data before it forwards the write request downstream.