In Versal devices, the intelligent pin selection (IPS) functionality provides mapping logic during implementation that attempts to route the reference clock to the desired PLL. The IPS provides a layer of mapping logic that assists the user to simplify design creation when multiple reference clocks are connected to any of the input ports on the desired PLL. This is shown in the example figure below.
The recommended procedure is to connect each reference clock input from top to bottom on the input multiplexer without leaving any gaps, as shown in the example figure above. IPS automatically provides the necessary mapping during implementation to make sure each of the reference clocks is correctly connected on the PLL input multiplexer.
The list below contains other restrictions or design practices that the user should follow:
- The design must connect the reference clock to the intended PLL.
- The user must configure the reference clock input multiplexer setting to match the reference clock input port that is required by the default line rate.
- The design must not instantiate IBUFDS_GTME5 at a location that violates the reference clock sharing rules. For more information, refer to Reference Clock Selection and Distribution.
- HSCLK*_LCPLLGTGREFCLK are reserved inputs and should not be used.