The transceiver RX datapath has two internal parallel clock domains used in the PCS: the PMA parallel clock domain (XCLK) and the fabric clock domain (RXUSRCLK). To receive data, the RX buffer provides data width conversion between these clock domains when necessary, depending on the operating data width and encoding mode. The following figure shows the RX datapath clock domains.
The GTM receiver includes an RX FIFO to support data width conversion when data crosses from the XCLK to RXUSRCLK domain. The buffer does not tolerate ppm differences and only provides phase compensation between the two clocks. The RX FIFO inside the GTM transceiver must always be used and cannot be bypassed.