RXUSRCLK Generation

Versal ACAP GTM Transceivers Architecture Manual (AM017)

Document ID
AM017
Release Date
2022-04-27
Revision
1.0 English

The RX Interface includes the parallel clock RXUSRCLK. RXUSRCLK is the internal clock for the PCS logic in the transmitter. The required rate for RXUSRCLK depends on the interface width of the GTME5_QUAD primitive and the RX line rate of the GTM transmitter. The following equation shows how to calculate the required rate for RXUSRCLK for all cases.

Figure 1. RXUSRCLK

RXUSRCLK is the main synchronization clock for all signals into the RX side of the GTM transceiver. Most signals into the RX side of the GTM transceiver are sampled on the positive edge of RXUSRCLK.