The Versal ACAP transceivers provide different reference clock input options. Clock selection supports two LCPLLs.
From an architecture perspective, a Quad (or Q) contains four channels, two HSCLK blocks, two dedicated external reference clock pin pairs, and dedicated reference clock routing. An additional constraint on the above resources within a Quad is that there is one LCPLL within each of the HSCLK0/1 blocks.
The GTME5_QUAD primitive must be instantiated when any PLL or transceiver channel inside the Quad is used. For duals operating at line rates from 9.5 Gb/s to 29 Gb/s (NRZ) and 19 Gb/s to 56.42 Gb/s (PAM4), the reference clock for a Quad (Q(n)) can also be sourced from up to two Quads below (Q(n–1) or Q(n–2)) or from up to two Quads above (Q(n+1) or Q(n+2)). For devices that support stacked silicon interconnect (SSI) technology, the reference clock sharing is limited within its own super logic region (SLR).
See the Versal ACAP data sheets for more information about SSI technology.
Each Quad has two dedicated differential reference clock input pins (MGTREFCLK[P/N]0 or MGTREFCLK[P/N]1) that can be connected to the external clock sources. In a single external reference use model, an IBUFDS_GTME5 must be instantiated to use one of the dedicated differential reference clock sources. The following figure shows a single external reference clock connected to multiple transceivers within a single Quad. The user design connects the IBUFDS_GTME5 output (O) to the corresponding HSCLK[0/1]_LCPLLGTREFCLK[0/1] ports of the GTME5_QUAD for the GTM transceiver.
For Versal devices, sourcing of the reference clock is limited to two Quads above and below for duals operating at line rates from 9.5 Gb/s to 29 Gb/s (NRZ) and 19 Gb/s to 56.42 Gb/s (PAM4). Channels should source a local reference clock (from within its own Quad) for highest performance.
Reference clock features include:
- Clock routing for northbound and southbound clocks.
- Flexible clock inputs available for the LCPLL.
- Static or dynamic selection of the reference clock for the LCPLL.
The Quad architecture has four GTM transceivers, two dedicated reference clock pin pairs, and dedicated north or south reference clock routing. Each GTM transceiver channel in a Quad has six clock inputs available according to the corresponding PLL resource assignments shown in the following table.
|Clock Source||PLL Used||GTM Transceivers Channel 0/1||GTM Transceivers Channel 2/3|
|Two local reference clock pin pairs||LCPLL||
|Two reference clock pin pairs from Quads above||LCPLL||
|Two reference clock pin pairs from Quads below||LCPLL||
Because there are only two south clock inputs and four potential clock sources from the two Quads above (Q(n+1)) and Q(n+2)), only a maximum of two of the four potential reference clock pin pairs from above can be physically connected up to Q(n) at any given moment. The four potential reference clock pin pairs from above are reduced to two or three if the Quad above (Q(n+1)) is itself sourcing reference clock pin pairs from two above (Q(n+3)). This is because there are a total of two south reference clock routing tracks connecting the Quads. Similar rules apply when sourcing a reference clock from Quads below. Because there are two north clock inputs and four potential clock sources from the two Quads below (Q(n–1) and Q(n–2)), only a maximum of two of the four potential reference clock pin pairs from below can be physically connected up to Q(n) at any given moment. The four potential reference clock pin pairs from below is reduced to two or three if the Quad below (Q(n–1)) is itself sourcing reference clock pin pairs from two below Q(n–3). Again, this is because there are a total of two north reference clock routing tracks connecting the Quads. For example, Q(n–1) is sourcing both reference clocks from Q(n–3). In this example, Q(n) would only be able to source reference clock pins below from Q(n–1). Q(n) would not be able to access the reference clock pins in Q(n–2) because the two routing tracks have already been used to bring the two reference clocks from Q(n–3) to Q(n–1).
The following figure shows the detailed view of the reference clock multiplexer structure within a single HSCLK block, using LCPLL inside block HSCLK0 as an example. The same structure applies to LCPLL inside HSCLK1. When single or multiple reference clock sources are connected, the designer first needs to make sure that the connections are made to the correct PLLs using the reference clock ports assigned to the each intended PLL. The enhanced intelligent pin selection (IPS) automatically analyzes the design and maps reference clock selection during design implementation to guarantee that clocks are properly connected. For additional details on IPS, see Intelligent Pin Selection.
The following tables list the corresponding reference clock selection multiplexer settings.
|HSCLK[0/1]_LCPLLREFCLKSEL||HS[0/1]_LCPLL_IPS_REFCLK_SEL||Selected Input to LCPLL|
For HSCLK0: HSCLK0_LCPLLGTREFCLK0
For HSCLK1: HSCLK1_LCPLLGTREFCLK1
For HSCLK0: HSCLK0_LCPLLGTREFCLK1
For HSCLK1: HSCLK1_LCPLLGTREFCLK0
As shown in Figure 2, the GTM transceiver in Versal ACAPs contain multiple dedicated reference clock input ports for each PLL. The user should set the muxing of the reference clock input by using the selector port or the selector attribute. The following table lists the reference clock multiplexer selector control signals per PLL.
|PLL||Selector Control Attribute||Multiplexer Selector Port/Attribute|
|LCPLL (HSCLK0)||HS0_LCPLL_IPS_PIN_EN =
|LCPLL (HSCLK1)||HS1_LCPLL_IPS_PIN_EN =