The simulation environment and the test bench must fulfill specific prerequisites before running simulation using the GTME5_QUAD primitives. For instructions on how to set up the simulation environment for supported simulators depending on the used hardware description language (HDL) used, see the Vivado Design Suite User Guide: Logic Simulation (UG900).
The prerequisites for simulating a design with the GTME5_QUAD primitives are as follows:
- A simulator with support for Secure IP models: SecureIP is an IP encryption methodology. SecureIP models are encrypted versions of the System Verilog HDL used for implementation of the modeled block. To support SecureIP models, a simulator that complies with the encryption standards described in the IEEE Standard for Verilog Hardware Description Language (IEEE Std 1364-2005) is required.
- A mixed-language simulator for VHDL simulation: SecureIP models use a System Verilog standard. To use them in a VHDL design, a mixed-language simulator is required. The simulator must be able to simulate VHDL and Verilog simultaneously.
- An installed GTM transceiver SecureIP model.
- The correct setup of the simulator for SecureIP use (initialization file, environment variables).
- The correct simulator resolution (Verilog).