Pseudo-random sequences (PRBS) are commonly used to test the signal integrity of high-speed links. These sequences appear random but have specific properties that can be used to measure the quality of a link. The GTM transceiver pattern generator block can generate several industry-standard PRBS patterns listed in the following table.
|Name||Polynomial||Length of Sequence||Description|
|PRBS-7||1 + x6 + x7||27 – 1 bits||Used to test channels with 8B/10B.|
|PRBS-9||1 + x5 + x9||29 – 1 bits||ITU-T Recommendation O.150, Section 5.1. PRBS-9 is one of the recommended test patterns for SFP+.|
|PRBS-13||1 + x + x2 + x12 + x13||29 – 1 bits||IEEE Std P802.3bs 126.96.36.199.1 test requires PRBS13Q test pattern. OIF2014.230 CEI-56G-VSR-PAM4 specification requires QPRBS13-CEI test pattern.|
|PRBS-15||1 + x14 + x15||215 – 1 bits||ITU-T Recommendation O.150, Section 5.3. PRBS-15 is often used for jitter measurement because it is the longest pattern the Agilent DCA-J sampling scope can handle.|
|PRBS-23||1 + x18 + x23||223 – 1 bits||ITU-T Recommendation O.150, Section 5.6. PRBS-23 is often used for non-8B/10B encoding schemes. It is one of the recommended test patterns in the SONET specification.|
|PRBS-31||1 + x28 + x31||231 – 1 bits||ITU-T Recommendation O.150, Section 5.8. PRBS-31 is often used for non-8B/10B encoding schemes. It is a recommended PRBS test pattern for 10 Gigabit Ethernet. See IEEE Std 802.3ae-2002. IEEE Std P802.3bs188.8.131.52.2 test requires PRBS31Q test pattern.|
In addition to PRBS patterns, the GTM transceiver supports a 64 UI
square wave test pattern as shown in the following figure, an alternating
clock) test pattern. Clocking patterns are usually used to check PLL random jitter
often done with a spectrum analyzer.
1'b1test pattern will not be a square wave due to the amplitude modulation mapping.
The error insertion function is also supported to verify link connection for jitter tolerance tests. When an inverted PRBS pattern is necessary, the CH[0/1]_TXPOLARITY signal is used to control polarity.
The pattern generator might control when an injection of an error in the generated pattern occurs by choosing between two modes. In LEVEL mode, the generator injects an error after any cycle in which CH*_TXPRBSFORCEERR is High. In EDGE mode, an error is injected only after CH*_TXPRBSFORCEERR has just gone High after being Low in the previous cycle. The mode selection can be done using the TX_PRBS_FORCE_MODE attribute. The following figure shows the error injection in both operating modes.