The TX programmable divider shown in TX Fabric Clock Output Control uses the PLL output clock to generate a
parallel output clock. By using the transceiver PLL, TX programmable divider, and BUFG_GT,
CH*_TXOUTCLK (TXOUTCLKCTL = 3'b101) can be used as a clock
source for the interconnect logic. The supported divider values are 4, 5, 5.5, 8, 10, 16,
16.5, 20, 32, 33, 40, 64, and 66.