The following figure shows the write transfer timing diagram.
At T1, a write transfer starts with address APB3PADDR, write data APB3PWDATA, write signal APB3PWRITE, and select signal APB3PSEL, being registered at the rising edge of APB3CLK. This is called the Setup phase of the write transfer.
At T2, enable signal APB3PENABLE and ready signal APB3PREADY are registered at the rising edge of APB3CLK. When asserted, APB3PENABLE indicates the start of the Access phase of the transfer. When asserted, APB3PREADY indicates that the slave can complete the transfer at the next rising edge of APB3CLK.
The address APB3PADDR, write data APB3PWDATA, and control signals all remain valid until the transfer completes at T3, the end of the Access phase.
The enable signal APB3PENABLE is deasserted at the end of the transfer. The select signal APB3PSEL is also deasserted unless the transfer is to be followed immediately by another transfer to the same peripheral.
The timing of the address, write, select, and enable signals are as described for write transfers. The slave must provide the data before the end of the read transfer.