BISC_RL_DLY_QTR_11 (DDRMC_DDR4_XRAM) Register Description
Register Name | BISC_RL_DLY_QTR_11 |
Offset Address | 0x0000000B44 |
Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
|
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Delay Per Quarter Period |
Number of fine taps for 1/4 of the memory clock period. One per nibble.
BISC_RL_DLY_QTR_11 (DDRMC_DDR4_XRAM) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
Value | 8:0 | roRead-only | 0x0 | Delay Per Quarter Period |