BISC_RL_DLY_QTR_15 (DDRMC_LPDDR4_XRAM) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

BISC_RL_DLY_QTR_15 (DDRMC_LPDDR4_XRAM) Register Description

Register NameBISC_RL_DLY_QTR_15
Offset Address0x0000000B54
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionDelay Per Quarter Period

Number of fine taps for 1/4 of the memory clock period. One per nibble.

BISC_RL_DLY_QTR_15 (DDRMC_LPDDR4_XRAM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Value 8:0roRead-only0x0Delay Per Quarter Period