F0_CALBISC_RL_DLY_NQTR_15 (DDRMC_DDR4_XRAM) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

F0_CALBISC_RL_DLY_NQTR_15 (DDRMC_DDR4_XRAM) Register Description

Register NameF0_CALBISC_RL_DLY_NQTR_15
Offset Address0x000000492C
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionBISC Quarter Period Taps, Falling Edge

Number of taps for a quarter clock cycle, falling edge. Permuted by byte lanes.

F0_CALBISC_RL_DLY_NQTR_15 (DDRMC_DDR4_XRAM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Value 8:0roRead-only0x0BISC Quarter Period Taps, Falling Edge