F0_DB_DWL_MWD_LAT_18 (DDRMC_DDR4_XRAM) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

F0_DB_DWL_MWD_LAT_18 (DDRMC_DDR4_XRAM) Register Description

Register NameF0_DB_DWL_MWD_LAT_18
Offset Address0x0000004BC0
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionData Buffer Write Latency

F0_DB_DWL_MWD_LAT_18 (DDRMC_DDR4_XRAM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
db_latency 8:6roRead-only0x0LRDIMM Data Buffer Latency
db_phase 5:0roRead-only0x0LRDIMM Data Buffer Phase