F0_DB_DWL_MWD_LAT_34 (DDRMC_DDR4_XRAM) Register Description
Register Name | F0_DB_DWL_MWD_LAT_34 |
---|---|
Offset Address | 0x0000004C00 |
Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Data Buffer Write Latency |
F0_DB_DWL_MWD_LAT_34 (DDRMC_DDR4_XRAM) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
db_latency | 8:6 | roRead-only | 0x0 | LRDIMM Data Buffer Latency |
db_phase | 5:0 | roRead-only | 0x0 | LRDIMM Data Buffer Phase |